TTTC: DFT 2012 Call for Papers - Submission Deadline May 6th!

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The topics include (but are not limited to) the following ones:

1. Yield Analysis and Modeling
Defect/Fault analysis and models; statistical yield modeling; critical area and metrics.

2. Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.

3. Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques.

4. Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization.

5. Defect and Fault Tolerance
Reliable circuit/system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors.

6. Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors.

7. Repair, Restructuring and Reconfiguration
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing.

8. Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks.

9. Emerging Technologies
Techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.

10. Hardware security
Fault attacks, fault tolerance-based countermeasures, Scan-based attacks and countermeasures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and reliability

Submissions

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Prospective authors are invited to submit original and unpublished contributions (6 pages - with the opportunity to purchase 2 additional ones - in the IEEE conference template, 2-columns style, available on conference web site), to be submitted as PDF file. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:

http://www.dfts.org

We are also interested in panel sessions that involve industrial experiences: please send an email to the Program co-Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.

Paper Publication and Author Registration: Only original, unpublished work will be accepted, for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society and will appear in the Digital Library.

Every accepted paper MUST have at least one full paid registration by the time the camera-ready paper is submitted for inclusion in the proceedings. The author is also expected to attend the Symposium and present the paper.

Best Student Paper Award: All papers with a student as both primary author and presenter will be taken into consideration for the 2012 Best Student Paper Award, sponsored by Intel.

Journal Special Issue: There will be a possibility for the authors of selected papers presented at DFT 2012 to submit an extended version of their work in a special issue of an archival journal.

Key Dates

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Submission deadline: May 6, 2012
Notification of acceptance: July 1, 2012
Final copy deadline: August 3, 2012

Additional Information

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General co-Chairs
Prashant D. Joshi
Intel, U.S.A
E-mail: prashant.d.joshi@intel.com

Massimo Violante
Politecnico di Torino, Italy
E-mail: massimo.violante@polito.it

Program co-Chairs
Jie Han
University of Alberta, Canada
E-mail: jhan8@ualberta.ca

Ramesh Karri
Polytechnic Institute of NYU, U.S.A
E-mail: rkarri@poly.edu

Committees

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General co-Chairs
Prashant D. Joshi
Intel, U.S.A
E-mail: prashant.d.joshi@intel.com

Massimo Violante
Politecnico di Torino, Italy
E-mail: massimo.violante@polito.it

Program co-Chairs
Jie Han
University of Alberta, Canada
E-mail: jhan8@ualberta.ca

Ramesh Karri
Polytechnic Institute of NYU, U.S.A
E-mail: rkarri@poly.edu

Publicity Chair
Antonio Miele
Politecnico di Milano, Italy
E-mail: miele@elet.polimi.it

Technical Program Committee
M. A. Aguirre Echanove, University of Seville
P. Ampadu, University of Rochester
C. Bolchini, Politecnico di Milano
S. Chakravarty, LSI Logic
G. Chapman, Simon Fraser University
L. Chen, University of Saskatchewan
Y. Choi, Hongik University
A. Daniel, Intel
L. Dilillo, LIRMM
B. Eklow, CISCO
M. Favalli, University of Ferrara
M. Fukushi, Tohoku University
D. Gizopoulos, University of Piraeus
S. Hamdioui, Delft University of Technology
C. Huang, Nat’l Tsing Hua U.
A. Jas, Intel
N. Jha, Princeton
W. Jone, University of Cincinnati
Y. Kim, Northeastern University
I. Koren, UMASS Amherst
R. Leveugle, TIMA labs
X. Li, Chinese Academy of Science
H. Li, Chinese Academy of Science
F. Lombardi, Northeastern University
Y. Makris, UT Dallas
C. Metra, University of Bologna
F. Miller, EADS
K. Namba, Chiba University
N. Nicolici, McMaster University
M. Ottavi, University of Rome “Tor Vergata”
N. Park, Oklahoma State University
A. Paschalis, University of Athens
Z. Peng, Linkoping University
W. Pleskacz, Warsaw U.T.
S. Pontarelli, University of Rome “Tor Vergata”
M. Rebaudengo, Politecnico di Torino
S. Reddy, University of Iowa
F. Salice, Politecnico di Milano
A. Salsano, University of Rome “Tor Vergata”
D. Sciuto, Politecnico di Milano
O. Sinanoglu, New York University
P. Song, IBM
M. Tehranipoor, University of ConnecticutJ. Teixeira, INESC-ID Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, University of Texas at Austin
S. Tragoudas, Southern Illinois Univ. Carbondale
R. Velazco, TIMA labs
D. Xiang, Tsinghua University
Q. Xu, Chinese University of Hong Kong
Q. Yu, University of New Hampshire
L. Wang, University of Connecticut
X. Wen, Kyushu Institute of Technology

For more information, visit us on the web at: http://www.dfts.org

The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).